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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC9443/D Rev 2, 05/2002
2.5V and 3.3V LVCMOS Clock Fanout Buffer
The MPC9443 is a 2.5V and 3.3V compatible 1:16 clock distribution buffer designed for low-voltage high-performance telecom, networking and computing applications. The device supports 3.3V, 2.5V and dual supply voltage (mixed-voltage) applications. The MPC9443 offers 16 low-skew outputs which are divided into 4 individually configurable banks. Each output bank can be individually supplied by 2.5V or 3.3V, individually set to run at 1X or 1/2X of the input clock frequency or be disabled (logic low output state). Two selectable LVPECL compatible inputs support differential clock distribution systems. In addition, one selectable LVCMOS input is provided for LVCMOS clock distribution systems. The MPC9443 is specified for the extended temperature range of -40 to +85C. Features * Configurable 16 outputs LVCMOS clock distribution buffer
MPC9443
LOW VOLTAGE SUPPLY 2.5V AND 3.3V LVCMOS CLOCK FANOUT BUFFER
* Compatible to single, dual and mixed 3.3V/2.5V voltage supply * Output clock frequency up to 350 MHz * Designed for high-performance telecom, networking and computer
applications * Supports applications requiring clock redundancy
FA SUFFIX 48-LEAD LQFP PACKAGE CASE 932-03
* * * * * *
Max. output skew of 250 ps (125 ps within one bank) Selectable output configurations per output bank Individually per-bank high-impedance tristate Output disable (stop in logic low state) control 48 ld LQFP package Ambient operating temperature range of -40 to 85C
Functional Description The MPC9443 is a full static design supporting clock frequencies up to 350 MHz. The signals are generated and retimed on-chip to ensure minimal skew between the four output banks. Two independent LVPECL compatible clock inputs are available. This feature supports redundant differential clock sources. In addition, the MPC9443 supports single-ended LVCMOS clock distribution systems. Each of the four output banks can be individually supplied by 2.5V or 3.3V, supporting mixed voltage applications. The FSELx pins choose between division of the input reference frequency by one or two. The frequency divider can be set individually for each output bank. The MPC9443 output banks are in high-impedance state by deasserting the OEN pins. Asserting OEN will the enable output banks. Please see the Output High-Impedance Control table on page 4 for details. The outputs can be synchronously stopped (logic low state). The outputs provide LVCMOS compatible levels with the capability to drive terminated 50 transmission lines. For series terminated transmission lines, each of the MPC9443 outputs can drive one or two traces giving the devices an effective fanout of 1:32 at VCC = 3.3V. The device is packaged in a 7x7 mm2 48-lead LQFP package.
(c) Motorola, Inc. 2002
1
MPC9443
(pulldown) (pullup) (pulldown) (pullup) (pulldown)
PCLK0 PCLK0 PCLK1 PCLK1 CCLK
0 0 1 1
Bank A CLK CLK / 2
0 1
QA0 QA1 QA2 QA3 QA4
PCLK_SEL CCLK_SEL
(pulldown) (pulldown) 0 1
Bank B
QB0 QB1 QB2
FSELA FSELB FSELC FSELD
(pulldown) (pulldown) (pulldown) (pulldown) 0
Bank C
QC0 QC1
1
QC2 QD0 Bank D
0
QD1 QD2
CLK_STOP OE0 OE1
(pulldown)
1
QD3 QD4
(pulldown) (pulldown)
5 Figure 1. MPC9443 Logic Diagram
VCCC VCCB GND GND GND VCC QC0 QC1 QC2 QB0 QB1 QB2
VCCA QA4 QA3 QA2 GND QA1 QA0 VCCA FSELA FSELB FSELC GND
37 38 39 40 41 42 43 44 45 46 47 48
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 1 VCC 2 FSELD 3 CCLK 4 CCLK_SEL 5 GND 6 PCLK0 7 PCLK0 8 VCC 9 PCLK_SEL 13 10 11 12 PCLK1 PCLK1 GND
VCCD QD0 QD1 QD2 GND QD3 QD4 VCCD CLK_STOP OE0 OE1 GND
MPC9443
Figure 2. 48-Lead Package Pinout (Top View)
MOTOROLA
2
TIMING SOLUTIONS
MPC9443
Table 1: Pin Configuration
Pin CCLK PCLK0, PCLK0 PCLK1, PCLK1 FSELA, FSELB, FSELC, FSELD CCLK_SEL PCLK_SEL OE0, OE1 CLK_STOP GND VCCA, VCCB, VCCC, VCCD VCC QA0 to QA4 QB0 to QB2 QC0 to QC2 QD0 to QD4 Output Output Output Output Input Input Input Input Input Input Input Input I/O Type LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Supply Supply Supply LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS clock inputs LVPECL differential clock input LVPECL differential clock input Output bank divide select input LVCMOS/LVPECL clock input select PCLK0/PCLK1 clock input select Output tristate control Synchronous output enable/disable (clock stop) control Negative voltage supply Positive voltage supply output bank (VCC) Positive voltage supply core (VCC) Bank A outputs Bank B outputs Bank C outputs Bank D outputs Function
Table 2: Supported Single and Dual Supply Configurations
Supply voltage configuration 3.3V supply Mixed mode supply 2.5V supply a. b. c. d. e. VCCa 3.3V 3.3V 2.5V VCCAb 3.3V 3.3V or 2.5V 2.5V VCCBc 3.3V 3.3V or 2.5V 2.5V VCCCd 3.3V 3.3V or 2.5V 2.5V VCCDe 3.3V 3.3V or 2.5V 2.5V GND 0V 0V 0V
VCC is the positive power supply of the device core and input circuitry. VCC voltage defines the input threshold and levels VCCA is the positive power supply of the bank A outputs. VCCA voltage defines bank A output levels VCCB is the positive power supply of the bank B outputs. VCCB voltage defines bank B output levels VCCC is the positive power supply of the bank C outputs. VCCC voltage defines bank C output levels VCCD is the positive power supply of the bank D outputs. VCCD voltage defines bank D output levels
Table 3: Function Table (Controls)
Control CCLK_SEL PCLK_SEL FSELA FSELB FSELC FSELD CLK_STOP OE0, OE1 Default 0 0 0 0 0 0 0 00 0 PCLK or PCLK1 active (LVPECL clock mode) PCLK0 active, PCLK1 inactive fQA0:4 = fREF fQB0:2 = fREF fQC0:2 = fREF fQD0:4 = fREF Normal operation 1 CCLK active (LVCMOS clock mode) PCLK1 active, PCLK0 inactive fQA0:4 = fREF / 2 fQB0:2 = fREF / 2 fQC0:2 = fREF / 2 fQD0:4 = fREF / 2 Outputs are synchronously disabled (stopped) in logic low state Asynchronous output enable control. See Table 4. OEN
TIMING SOLUTIONS
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MOTOROLA
MPC9443
Table 4: Output High-Impedance Control (OEN)a
OE0 0 0 1 1 a. 0 1 0 1 OE1 QA0 to QA4 Enabled Enabled Enabled Disabled (tristate) QB0 to QB2 Enabled Disabled (tristate) Enabled Disabled (tristate) QC0 to QC2 Enabled Disabled (tristate) Disabled (tristate) Disabled (tristate) QD0 to QD4 Enabled Enabled Disabled (tristate) Disabled (tristate) Total number of enabled outputs 16 10 8 0
OEN will tristate (high impedance) output banks independent on the logic state of the output and the status of CLK_STOP.
Table 5: Absolute Maximum Ratingsa
Symbol VCC VIN VOUT IIN IOUT TS Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Storage temperature -65 Characteristics Min -0.3 -0.3 -0.3 Max 3.6 VCC+0.3 VCC+0.3 20 50 125 Unit V V V mA mA C Condition
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied.
Table 6: General Specifications
Symbol VTT MM HBM LU CPD CIN Characteristics Output termination voltage ESD protection (Machine model) ESD protection (Human body model) Latch-up immunity Power dissipation capacitance Input capacitance 200 2000 200 10 4.0 Min Typ VCC / 2 Max Unit V V V mA pF pF Per output Condition
MOTOROLA
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TIMING SOLUTIONS
MPC9443
Table 7: DC Characteristics (VCC = VCCA = VCCB = VCCC = VCCD = 3.3V
Symbol VIH VIL VPP VCMRa IIN VOH VOL ZOUT ICCQd a. b. c. Characteristics Input High Voltage Input Low Voltage Peak-to-peak Input Voltage Common Mode Range Input Currentb Output High Voltage Output Low Voltage Output Impedance 19 PCLK0, 1 PCLK0, 1 Min 2.0 -0.3 250 1.1 2.4 0.55 0.30 VCC-0.6 200 Typ
5%, TA = -40 to +85C)
Max VCC + 0.3 0.8 Unit V V mV V A V V V Condition LVCMOS LVCMOS LVPECL LVPECL VIN=GND or VIN=VCC IOH=-24 mAc IOL= 24mAc IOL= 12mA
W
d.
Maximum Quiescent Supply Current 2.0 mA All VCC Pins VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. Input pull-up / pull-down resistors influence input current. The MPC9443 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines (for VCC=3.3V) or one 50 series terminated transmission line (for VCC=2.5V). ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
Table 8: AC Characteristics (VCC = VCCA = VCCB = VCCC = VCCD = 3.3V
Symbol fref fMAX VPP VCMRb tP, REF tr, tf tPLH tPHL tPLH tPHL tPLZ, HZ tPZL, LZ tS, tH tsk(LH, HL) Input Frequency Maximum Output Frequency Peak-to-peak Input Voltage Common Mode Range Reference Input Pulse Width CCLK Input Rise/Fall Time Propagation Delay PCLK0,1 to any Q PCLK0,1 to any Q CCLK to any Q CCLK to any Q 2.5 2.4 2.1 1.9 /1 output /2 output PCLK0,1 PCLK0,1 Characteristics Min 0 0 0 500 1.3 1.4
5%, TA = -40 to +85C)a
Max 350 350 175 1000 VCC-0.8 1.0c 5.0 5.2 4.2 4.6 10 10 Unit MHz MHz MHz mV V ns ns ns ns ns ns ns ns ps 125 225 250 2.5 2.1 2.8 2.7 300 400 ps ps ps ns ns ns ns ps ps % % DCREF = 50% 0.8 to 2.0V FSELx=0 FSELx=1 LVPECL LVPECL Condition
Typ
Output Disable Time Output Enable Time Setup, hold time (reference clock to CLK_STOP) Output-to-output Skewd Within one bank Any output, same output divider Any output, any output divider Device-to-device Skew (LH)e Using PCLK0,1 Using CCLK Device-to-device Skew (LH, HL)f Using PCLK0,1 Using CCLK Output pulse skewg Using PCLK0,1 Using CCLK Output Duty Cycle fQ<140 MHz and using CCLK fQ<250 MHz and using PCLK0,1 Output Rise/Fall Time 45 45 50 50 500
tsk(PP)
tSK(P)
DCQ
55 55
a. b. c. d. e. f. g.
tr, tf 0.1 1.0 ns 0.55 to 2.4V AC characteristics apply for parallel output termination of 50 to VTT. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. tsk(LH, HL) includes both device skew referenced to the rising output edge and device skew referenced to the falling output edge. Device-to-device skew referenced to the rising output edge. Device-to-device skew referenced to the rising output edge or referenced to the falling output edge. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |.
TIMING SOLUTIONS
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MOTOROLA
MPC9443
Table 9: DC Characteristics (VCC = VCCA = VCCB = VCCC = VCCD = 2.5V
Symbol VIH VIL VPP VCMRa IIN VOH VOL Characteristics Input High Voltage Input Low Voltage Peak-to-peak Input Voltage Common Mode Range Input Currentb Output High Voltage Output Low Voltage PCLK0,1 PCLK0,1 Min 1.7 -0.3 250 1.1 1.8 0.6 VCC-0.7 200 Typ
5%, TA = -40 to +85C)
Max VCC + 0.3 0.7 Unit V V mV V A V V Condition LVCMOS LVCMOS LVPECL LVPECL VIN=GND or VIN=VCC IOH= -15 mAc IOL= 15 mAc
ZOUT Output Impedance 22 ICCQd Maximum Quiescent Supply Current 2.0 mA All VCC Pins a. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. b. Input pull-up / pull-down resistors influence input current. c. The MPC9443 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives one 50 series terminated transmission lines at VCC=2.5V. d. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
W
Table 10: AC Characteristics (VCC = VCCA = VCCB = VCCC = VCCD = 2.5
Symbol fref fMAX VPP VCMRb tP, REF tr, tf tPLH tPHL tPLH tPHL tPLZ, HZ tPZL, LZ tS, tH tsk(LH, HL) Input Frequency Maximum Output Frequency Peak-to-peak input voltage Common Mode Range Reference Input Pulse Width CCLK Input Rise/Fall Time Propagation delay PCLK0,1 to any Q PCLK0,1 to any Q CCLK to any Q CCLK to any Q 2.8 2.7 2.2 2.1 /1 output /2 output PCLK0,1 PCLK0,1 Characteristics Min 0 0 0 500 1.1 1.4
5%, TA = -40 to +85C)a
Max 350 350 175 1000 VCC-0.7 1.0c 6.0 6.2 5.3 5.5 10 10 Unit MHz MHz MHz mV V ns ns ns ns ns ns ns ns ps 125 225 250 3.2 3.1 3.5 3.4 300 400 ps ps ps ns ns ns ns ps ps % % DCREF = 50% 0.8 to 2.0V FSELx=0 FSELx=1 LVPECL LVPECL Condition
Typ
Output Disable Time Output Enable Time Setup, hold time (reference clock to CLK_STOP) Output-to-output Skewd Within one bank Any output, same output divider Any output, any output divider Device-to-device Skew (LH)e Using PCLK0,1 Using CCLK Device-to-device Skew (LH, HL)f Using PCLK0,1 Using CCLK g Output pulse skew Using PCLK0,1 Using CCLK Output Duty Cycle fQ<140 MHz and using CCLK fQ<250 MHz and using PCLK0,1 Output Rise/Fall Time 500
tsk(PP)
tSK(p)
DCQ
45 45
50 50
55 55
a. b. c. d. e. f. g.
tr, tf 0.1 1.0 ns 0.6 to 1.8V AC characteristics apply for parallel output termination of 50 to VTT. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. tsk(LH, HL) includes both device skew referenced to the rising output edge and device skew referenced to the falling output edge. Device-to-device skew referenced to the rising output edge. Device-to-device skew referenced to the rising output edge or referenced to the falling output edge. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |.
MOTOROLA
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TIMING SOLUTIONS
MPC9443
Table 11: DC Characteristics (VCC = 3.3V 5%, any VCCA,B,C,D = 2.5V
Symbol VIH VIL IIN VOH VOL VPP VCMRc ZOUT Characteristics Input high voltage Input low voltage Input currenta Output High Voltage Output Low Voltage Peak-to-peak input voltage Common Mode Range Output impedance 2.5V output 3.3V output 2.5V output 3.3V output PCLK0,1 PCLK0,1 2.5V output 3.3V output 250 1.1 22 19 VCC-0.6
5% or 3.3V 5% (mixed), TA = -40 to +85C)
Min 2.0 -0.3 1.7 2.0 0.6 0.55 Typ Max VCC + 0.3 0.8 200 Unit V V A V V mV IOH= -15 mAb IOH= -24 mAb IOL= 15 mAb IOL= 24 mAb LVPECL LVPECL Condition LVCMOS LVCMOS
W W
V
CPD Power Dissipation Capacitance 10 pF Per Output ICCQd Maximum Quiescent Supply Current 2.0 mA All VCC Pins a. Input pull-up / pull-down resistors influence input current. b. The MPC9443 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines (for VCC=3.3V) or one 50 series terminated transmission line (for VCC=2.5V). c. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. d. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
Table 12: AC Characteristics (VCC = 3.3V 5%, any VCCA,B,C,D = 2.5V
Symbol tsk(LH, HL) tsk(PP) tPLH, HL tSK(P)
5% or 3.3V 5% (mixed), TA = -40 to +85C)a b
Min Typ Max 275 350 See 3.3V AC table See 3.3V AC table Using PCLK0,1 Using CCLK 400 500 ps ps DCREF = 50% Unit ps ps Condition
Characteristics Output-to-output SkewcAny output, same output divider Any output, any output divider Device-to-device Skew Propogation Delay Output pulse skewd
DCQ a. b. c. d.
45 50 fQ<140 MHz and using CCLK 55 % 45 50 fQ<250 MHz and using PCLK0,1 55 % AC characteristics apply for parallel output termination of 50 to VTT. This table only specifies AC parameter im mixed voltage supply conditions that vary from the corresponding AC tables. All other parameters, see the 3.3V (for 3.3V outputs) or 2.5V AC table (for 2.5V outputs). tsk(LH, HL) includes both device skew referenced to the rising output edge and device skew referenced to the falling output edge. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |. Output Duty Cycle
TIMING SOLUTIONS
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MOTOROLA
MPC9443
APPLICATIONS INFORMATION
Driving Transmission Lines The MPC9443 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines at VCC = 3.3V. For more information on transmission lines the reader is referred to application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9443 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 3. "Single versus Dual Transmission Lines" illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9443 clock driver is effectively doubled due to its capability to drive multiple lines (at VCC = 3.3V).
MPC9443 OUTPUT BUFFER IN
19
impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: = VS ( Z0 / (RS+R0 +Z0)) = 50 || 50 = 31 || 31 = 19 = 3.0 ( 25 / (15.5+19+25) = 1.26V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.52V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). VL Z0 RS R0 VL
3.0 OutA tD = 3.8956 OutB tD = 3.9386
2.5
VOLTAGE (V)
2.0 In 1.5
1.0
0.5 RS = 31 ZO = 50 OutA
0 2 4 6 8 TIME (nS) 10 12 14
MPC9443 OUTPUT BUFFER IN
19
Figure 4. Single versus Dual Waveforms
RS = 31 ZO = 50 OutB0
RS = 31
ZO = 50 OutB1
Figure 3. Single versus Dual Transmission Lines The waveform plots in Figure 4. "Single versus Dual Line Termination Waveforms" show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9443 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9443. The output waveform in Figure 4. "Single versus Dual Line Termination Waveforms" shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 31 series resistor plus the output
Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 5. "Optimized Dual Line Termination" should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched.
MPC9443 OUTPUT BUFFER
19
RS = 12
ZO = 50
RS = 12
ZO = 50
19 + 12 k 12 = 50 k 50 25 = 25 Figure 5. Optimized Dual Line Termination
MOTOROLA
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TIMING SOLUTIONS
MPC9443
Power Consumption of the MPC9443 and Thermal Management The MPC9443 AC specification is guaranteed for the entire operating frequency range up to 350 MHz. The MPC9443 power consumption and the associated long-term reliability may decrease the maximum frequency limit, depending on operating conditions such as clock frequency, supply voltage, output loading, ambient temperture, vertical convection and thermal conductivity of package and board. This section describes the impact of these parameters on the junction temperature and gives a guideline to estimate the MPC9443 die junction temperature and the associated device reliability. For a complete analysis of power consumption as a function of operating conditions and associated long term device reliability please refer to the application note AN1545. According the AN1545, the long-term device reliability is a function of the die junction temperature: Table 13: Die junction temperature and MTBF
Junction temperature (C) 100 110 120 130 MTBF (Years) 20.4 9.1 4.2 2.0 Still air 100 lfpm 200 lfpm 300 lfpm 400 lfpm 500 lfpm 64 50
In equation 2, P stands for the number of outputs with a parallel or thevenin termination, VOL, IOL, VOH and IOH are a function of the output termination technique and DCQ is the clock signal duty cyle. If transmission lines are used CL is zero in equation 2 and can be eliminated. In general, the use of controlled transmission line techniques eliminates the impact of the lumped capacitive loads at the end lines and greatly reduces the power dissipation of the device. Equation 3 describes the die junction temperature TJ as a function of the power consumption. Where Rthja is the thermal impedance of the package (junction to ambient) and TA is the ambient temperature. According to Table 13, the junction temperature can be used to estimate the long-term device reliability. Further, combining equation 1 and equation 2 results in a maximum operating frequency for the MPC9443 in a series terminated transmission line system. TJ,MAX should be selected according to the MTBF system requirements and Table 13. Rthja can be derived from Table 14. The Rthja represent data based on 1S2P boards, using 2S2P boards will result in a lower thermal impedance than indicated below. Table 14: Thermal package impedance of the 48ld LQFP
Convection, LFPM Rthja (1P2S board), K/W 69 Rthja (2P2S board), K/W 53
Increased power consumption will increase the die junction temperature and impact the device reliability (MTBF). According to the system-defined tolerable MTBF, the die junction temperature of the MPC9443 needs to be controlled and the thermal impedance of the board/package should be optimized. The power dissipated in the MPC9443 is represented in equation 1. Where ICCQ is the static current consumption of the MPC9443, CPD is the power dissipation capacitance per output, ()CL represents the external capacitive output load, N is the number of active outputs (N is always 16 in case of the MPC9443). The MPC9443 supports driving transmission lines to maintain high signal integrity and tight timing parameters. Any transmission line will hide the lumped capacitive load at the end of the board trace, therefore, CL is zero for controlled transmission line systems and can be eliminated from equation 1. Using parallel termination output termination results in equation 2 for power dissipation. P TOT
If the calculated maximum frequency is below 250 MHz, it becomes the upper clock speed limit for the given application conditions. The following eight derating charts describe the safe frequency operation range for the MPC9443. The charts were calculated for a maximum tolerable die junction temperature of 110C (120C), corresponding to an estimated MTBF of 9.1 years (4 years), a supply voltage of 3.3V and series terminated transmission line or capacitive loading. Depending on a given set of these operating conditions and the available device convection a decision on the maximum operating frequency can be made. CL
M
+
ICCQ
)V @ f
CC
CLOCK
@ N@C )
PD
@V
OH
CC
Equation 1
P TOT
+V @
CC
ICCQ
)V @ f
CC
CLOCK
@ N@C )
PD
CL
M
)
thja
DC Q
P
@ I @ V *V ) 1 *DC @ I @ V
CC OH Q OL
OL
Equation 2
TJ
+ T )P @ R
A TOT 2 CC
Equation 3
fCLOCK,MAX
1 +C @N@V @
PD
T J,MAX R thja
*T * I @ V
A CCQ
CC
Equation 4
TIMING SOLUTIONS
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MOTOROLA
MPC9443
Figure 6. Maximum MPC9443 frequency, VCC = 3.3V, MTBF 9.1 years, driving series terminated transmission lines
Figure 7. Maximum MPC9443 frequency, VCC = 3.3V, MTBF 9.1 years, 4 pF load per line
Figure 8. Maximum MPC9443 frequency, VCC = 3.3V, MTBF 4 years, driving series terminated transmission lines
Figure 9. Maximum MPC9443 frequency, VCC = 3.3V, MTBF 4 years, 4 pF load per line
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TIMING SOLUTIONS
MPC9443
DUT MPC9443 Pulse Generator Z = 50W ZO = 50 ZO = 50
RT = 50 VTT
RT = 50 VTT
Figure 10. CCLK MPC9443 AC test reference for Vcc = 3.3V and Vcc = 2.5V
DUT MPC9443 Differential Pulse Generator Z = 50W ZO = 50 ZO = 50
RT = 50 VTT
RT = 50 VTT
Figure 11. PCLK MPC9443 AC test reference
PCLK PCLK VPP VCMR VCC VCC t(LH) t(HL)
CCLK
VCC VCC VCC VCC
B2 B2
GND
QX
B2
QX
GND t(LH) t(HL)
GND
Figure 12. Propagation delay (tPD) test reference
Figure 13. Propagation delay (tPD) test reference
VCC VCC
B2 B2
CCLK
VCC VCC VCC VCC
B2 B2
GND VOH VCC QX
GND
GND tSK(LH) tSK(HL) t(LH) t(HL)
GND
The pin-to-pin skew is defined as the worst case difference in propagation delay between any two similar delay paths within a single device
tSK(P) = | tPLH - tPHL |
Figure 14. Output-to-output Skew tSK(LH, HL)
Figure 15. Output Pulse Skew tSK(P) test reference
TIMING SOLUTIONS
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MPC9443
VCC VCC tP T0 DC = tP /T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage
B2
VCC=3.3V 2.4 0.55 tF tR VCC=2.5V 1.8V 0.6V
GND
Figure 16. Output Duty Cycle (DC)
Figure 17. Output Transition Time test reference
CCLK PCLK TJIT(CC) = |TN -TN+1 |
VCC VCC VCC VCC
B2 B2
GND
TN
TN+1
CLK_STOP
GND The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs tS tH
Figure 18. Cycle-to-cycle Jitter
Figure 19. Setup and hold time (tS, tH) test reference
MOTOROLA
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TIMING SOLUTIONS
MPC9443
OUTLINE DIMENSIONS
FA SUFFIX LQFP PACKAGE CASE 932-03 ISSUE F
4X
0.200 AB T-U Z 9 A1
48 37
A
DETAIL Y
P
1
36
T B B1
12 25
U V AE V1 AE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE AB IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS T, U, AND Z TO BE DETERMINED AT DATUM PLANE AB. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE AC. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE AB. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.350. 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076. 9. EXACT SHAPE OF EACH CORNER IS OPTIONAL. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.170 0.270 1.350 1.450 0.170 0.230 0.500 BSC 0.050 0.150 0.090 0.200 0.500 0.700 0_ 7_ 12 _REF 0.090 0.160 0.250 BSC 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF
13
24
Z S1 S
4X
T, U, Z DETAIL Y
0.200 AC T-U Z
AB
G
0.080 AC
AD AC
BASE METAL
DIM A A1 B B1 C D E F G H J K L M N P R S S1 V V1 W AA
M_
TOP & BOTTOM
R
GAUGE PLANE
0.080
SECTION AE-AE
TIMING SOLUTIONS
III III III III III
F D
M
C
E
AC T-U Z H DETAIL AD AA W K L_
13
0.250
N
J
MOTOROLA
MPC9443
NOTES
MOTOROLA
14
TIMING SOLUTIONS
MPC9443
NOTES
TIMING SOLUTIONS
15
MOTOROLA
MPC9443
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. MOTOROLA and the logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners.
E Motorola, Inc. 2002.
How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852-26668334 Technical Information Center: 1-800-521-6274 HOME PAGE: http://www.motorola.com/semiconductors/
MOTOROLA
16
MPC9443/D TIMING SOLUTIONS

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